Book: Uyemura Ch.7 pp.237–288 (PDF pp.253–305) · Quiz-2: 30 Oct 2026 · 10 marks · Jump to formula sheet → · 🖨️ Print

Electronic Analysis of CMOS Logic Gates — Quiz-2 Master Guide

Textbook: J.P. Uyemura, Introduction to VLSI Circuits and Systems, Chapter 7 (7.1–7.11). This guide teaches every section exactly as derived in the book, with equation numbers (7.x), textbook page figures, and a numerical after every topic.

🎯 Focus: numericals (VM, Rn/Rp, tr/tf, tp, Pdyn, sizing) 📕 Figs: direct page renders from your PDF 📋 Formula list for last-night revision 📝 Solved + unsolved drills

⚠️ Syllabus confusion cleared: your pasted list (7.1 Structured Procedures, D-Latch, JK-FF, MUX…) is Verilog-HDL Chapter 7 (lab / HDL topic), NOT this quiz. Quiz-2 per Course Plan (Lec 20–28) + the image you sent = Uyemura Ch.7 CMOS analysis. This guide covers Uyemura Ch.7 fully, + a 1-page topology-only primer of pre-midterm slides (low weightage) as you asked.

📌 Quiz scope & mark strategy

Course Plan 23ECE302 · Lectures 20–28 · CO2/CO3

Lecture	Topic (Course Plan wording)	Book section	Likely Q
20–21	DC switching characteristics of CMOS inverter — VTC, noise margins	7.1	VM numerical (Eq 7.14), VOH/VOL, NML/NMH — almost guaranteed 1Q
22–24	DC characteristics of NAND and NOR	7.4	Simultaneous-switching VM (7.94/7.97), left/right shift reason
25–27	Transient response of inverter — rise/fall, delay	7.2 + 7.5	Rn/Rp → tr/tf → fmax/tp; worst-case NAND/NOR — biggest marks
28	Power dissipation	7.3	Pdyn = C·V²·f, PDC — 1 short numerical
29–31 (spill)	Gate design for transient performance	7.7 (book) / Ch.8 start	Sizing: series n×, parallel 1×

Weightage read: Quiz-2 = 10 marks → 7.5% of internal. Expect ~2 numericals (4–5 marks each) or 1 numerical + 2 short theory. Pre-midterm slides (Ch 1/2/3/6) appear only as 1–2 topology/one-liner questions — don't sink time there.

⏱️ 60-minute fast path (if quiz is tomorrow)

Do in this order. Tick as you go.

15 min — §7.1: memorise Eq 7.14 (VM) + do Solved 7.1A below. Understand βn/βp → VM shift.
15 min — §7.2: memorise Rn/Rp (7.28), tr/tf=2.2τ, tp=0.69τ. Do Solved 7.2A (Ex 7.3 style).
10 min — §7.3: Pdyn=C·V²·f. Do 1 power sum.
10 min — §7.4 + 7.7: NAND shifts right (×1/N), NOR shifts left (×N); sizing series n×.
10 min — Read formula sheet aloud twice + attempt 2 unsolved in bank.

🧩 Primer: pre-midterm slides — topology only (low weightage)

Cover "topologically" as requested. One line each — enough for 1-mark questions.

Ch.1–2: CMOS inverter = pFET pull-up to VDD + nFET pull-down to GND. NAND = parallel p + series n. NOR = series p + parallel n. TG = n+p in parallel. Pass FET = single FET, suffers threshold drop.
Ch.3: Stick diagram / Euler path — just know pull-up vs pull-down duality; DRC = spacing/width rules (no numerical in Quiz-2).
Ch.6 (needed for Ch.7!): Square-law ID = (β/2)(VGS−VT)² (saturation, λ=0). β=k′(W/L), k′=μCox. FET RC model: ON FET ≈ resistor R=1/[β(VDD−VT)]; drain cap Cdb=Cj·Area+Cjsw·Perim. Elmore: series Rs add, internal caps add extra R·C term. If you know these 3, Ch.7 derivations click.
Verilog Ch.7 list you pasted (procedural assignments, D-latch/FF, JK-FF, counter, MUX/casex, loops) — not in this quiz; keep for lab/MH. If a 1-mark HDL Q sneaks in: blocking (=) vs non-blocking (<=), synchronous vs async clear, case vs casex (don't-cares) — that's all.

7.1 DC Characteristics of the CMOS Inverter (pp.237–244)

Book derivation exactly. Core = VTC + VM.

⬆ Textbook p.237 — Fig 7.1 CMOS inverter: βn=k′n(W/L)n, βp=k′p(W/L)p. Reference for every derivation.

⬆ Textbook p.238 — Fig 7.2 endpoints: Vin=0 → Vout=VDD; Vin=VDD → Vout=0.

⬆ Textbook p.239 — Fig 7.3 VTC: VOH, VOL, VIL/VIH at slope −1 points a/b, VM at Vout=Vin line.

Story in 4 lines

Slowly sweep Vin 0→VDD, record Vout → VTC. Ends are full-rail (CMOS superpower). Middle has two unity-gain points (slope −1) that define legal 0/1 input ranges and noise margins. The crossing with Vout=Vin line is VM (switching threshold) — set by βn/βp.

V_OH = V_DD (7.1)
V_OL = 0 V (7.2)
V_L = V_OH−V_OL = V_DD (full rail) (7.3)
V_GSn=V_in ; V_SGp=V_DD−V_in (7.4)
pFET cuts off when V_in=V_DD−|V_Tp| (7.5)

Logic-0 in: 0 < V_in < V_IL (7.6) · Logic-1 in: V_IH < V_in < V_DD (7.7)
NM_L=V_IL−V_OL ; NM_H=V_OH−V_IH (7.8)

Derivation of VM (the one they WILL ask) — Fig 7.4 logic:
1. Set V_in=V_out=V_M. KCL: I_Dn=I_Dp (7.9)
2. Prove both saturated: V_DSn=V_M > V_sat=V_M−V_Tn (since V_Tn>0) (7.10–7.11). Same for pFET.
3. Square-law (λ=0): (βn/2)(V_M−V_Tn)² = (βp/2)(V_DD−V_M−|V_Tp|)² (7.12)
4. √both sides: √(βn/βp)·(V_M−V_Tn) = V_DD−V_M−|V_Tp| (7.13)
5. Solve linear eq for V_M:

V_M = [V_DD − |V_Tp| + √(βn/βp)·V_Tn] / [1 + √(βn/βp)] (7.14) ⭐
βn/βp = [k′n(W/L)n]/[k′p(W/L)p] (7.15) · k′n/k′p = 2–3 (7.16)
Symmetric V_M=V_DD/2 needs βn=βp (if V_Tn=|V_Tp|) (7.18–7.20) → (W/L)p/(W/L)n = k′n/k′p ≈ 2.33

Intuition for viva: ↑(βn/βp) [stronger nFET] → VM shifts LEFT/down. ↓ratio → shifts right. Since μn≈2–3×μp, pFET must be ~2.5× wider for symmetric VTC. Symmetric = equal noise margins = most stable.

✅ Solved 7.1A — Ex 7.1 style (do this first)

Given: k′n=140, k′p=60 µA/V², VTn=0.7, |VTp|=0.7, VDD=3.0 V.

(a) Size for symmetric: need βn=βp → (W/L)p/(W/L)n = 140/60 = 2.33. So Wp≈2.33·Wn (same L). Then VM=VDD/2=1.50 V.

(b) Same sizes (W/L)p=(W/L)n: βn/βp=2.33, √=1.527. VM=(3.0−0.7+1.527·0.7)/(1+1.527)=(2.30+1.069)/2.527=≈1.33 V < 1.5 V. ✓ left shift.

✏️ Try yourself 7.1B (Problem [7.1])

k′n=100, VTn=0.70, k′p=42, VTp=−0.60, VDD=3.3, (W/L)n=10, (W/L)p=14. Find VM. Hint: βn=100·10=1000, βp=42·14=588, ratio=1.70, √=1.304 → VM≈?

Answer (verify): ≈1.42 V. Steps: (3.3−0.6+1.304·0.7)/(1+1.304)=(2.7+0.913)/2.304=3.613/2.304=1.568? Recompute carefully — see trap: |VTp|=0.6. (3.3−0.6=2.7). 2.7+0.913=3.613/2.304=1.57 V. (Recheck arithmetic in exam!)

7.2 Inverter Switching Characteristics (pp.244–257) — highest marks

RC model → exponential → tr/tf/tp. Memorise the chain.

⬆ Textbook — Fig 7.7 switching waveforms + Fig 7.8 FET→switch+R model.

⬆ Textbook — Fig 7.10 complete model: Cout = Cpar + CL, Cpar=Cdbn+Cdbp.

⬆ Textbook — Fig 7.12 fall: Cout discharges through Rn, Vout=VDD·e^(−t/τn).

⬆ Textbook — Fig 7.13 rise: Cout charges through Rp, Vout=VDD[1−e^(−t/τp)].

R_n = 1/[βn(V_DD−V_Tn)] ; R_p = 1/[βp(V_DD−|V_Tp|)] (7.28) ⭐
C_in=C_gn+C_gp (7.30) · C_L=FO·C_in (7.31)
C_out=C_par+C_L, C_par=C_dbn+C_dbp (7.32–7.33) ⭐

Fall derivation (memorise, 3 lines): i=−Cout·dVout/dt=Vout/Rn (7.42) → Vout(t)=VDD·e^(−t/τn), τn=Rn·Cout (7.43–7.44) → time 0.9→0.1: Δt=τn·ln(0.9/0.1)=τn·ln9≈2.2τn (7.45–7.48). Rise is mirror: tr≈2.2τp, τp=Rp·Cout (7.50–7.54).

t_f=t_PHL≈2.2·R_nC_out (7.48–7.49) · t_r=t_PLH≈2.2·R_pC_out (7.54)
f_max=1/(t_r+t_f) (7.55) · t_p=(t_PHL,50%+t_PLH,50%)/2, each 50% = ln2·τ≈0.69τ (7.64–7.66)

Linear form: t_r=t_r0+α_rC_L, t_f=t_f0+α_fC_L (7.69)
t_r0=2.2RpC_par, t_f0=2.2RnC_par (7.70) · α_r=2.2Rp, α_f=2.2Rn (7.71–7.72)
Symmetric (t_r=t_f): R_n=R_p → βn=βp if thresholds equal (7.81–7.84)

Trade-off line for theory Q: Bigger W → smaller R (faster slope α) BUT bigger Cpar (bigger intercept t0) + more area. "Fast circuits consume more area." Ratio βn/βp sets VM (DC); individual βn sets tf, βp sets tr.

✅ Solved 7.2A — Ex 7.3 style (exam template)

Given: (W/L)n=6,(W/L)p=8, k′n=150,k′p=62 µA/V², VTn=0.7,|VTp|=0.85, VDD=3.3, Cout=150 fF.

βp=62·8=496 µA/V². Rp=1/[496e-6·(3.3−0.85)]=1/1.215e-3=822.9 Ω. τp=822.9·150e-15=123.4 ps. tr=2.2·123.4=271.6 ps.

βn=150·6=900 µA/V². Rn=1/[900e-6·2.6]=427.4 Ω. τn=64.1 ps. tf=141.0 ps. fmax=1/(412.6ps)=2.42 GHz.

Note asymmetry (tr>tf) because pFET weaker — exactly what symmetric sizing fixes.

✏️ Try yourself 7.2B (Problem [7.3] c–d)

βn=2.1 mA/V², βp=1.8 mA/V², VTn=0.6, VTp=−0.7, VDD=5, Cpar=74 fF. (a) VM? (b) Rn,Rp? (c) tr,tf at CL=0? (d) at CL=115 fF?

Answers: (a) √(2.1/1.8)=1.08 → VM=(5−0.7+1.08·0.6)/2.08=(4.3+0.648)/2.08=2.38 V. (b) Rn=1/[2.1e-3·4.4]=108 Ω, Rp=1/[1.8e-3·4.3]=129 Ω. (c) tf0=2.2·108·74f=17.6 ps, tr0=2.2·129·74f=21.0 ps. (d) Cout=189 fF → tf=2.2·108·189f=44.9 ps, tr=53.6 ps.

7.3 Power Dissipation (pp.257–260)

Shortest section, 1 numerical. Derivation = charge per cycle.

⬆ Textbook — Fig 7.18 charge/discharge: first half charges Cout via pFET, second half discharges via nFET.

P = V_DDI_DD (7.85) = P_DC+P_dyn (7.86)
P_DC=V_DDI_DDq (leakage ~pA) (7.87)
Q_c=C_outV_DD (7.89) → P_av=V_DD(Q_c/T) (7.90)

P_dyn = C_outV_DD²f (7.91) ⭐ · P = P_DC+C_outV_DD²f (7.92)

One-liner: Energy per cycle = C·V²; power = energy × rate. Double f → double Pdyn. Dynamic dominates (µW vs pW). Later (7.6): with activity α, Pdyn=α·C·V²·f; NOR2/NAND2 α=3/16, XNOR α=1/4.

✅ Solved 7.3A

Cout=100 fF, VDD=5, f=100 MHz, IDDq=10 pA. Pdyn=100e-15·25·1e8=250 µW. PDC=5·10e-12=50 pW. Total≈250 µW (dynamic 10⁷× bigger).

At 1 GHz → 2.5 mW. For 1 mW need f=1e-3/(100e-15·25)=400 MHz.

✏️ Try yourself 7.3B

Cout=80 fF, VDD=3.3 V, f=500 MHz. Find Pdyn. Ans: 80e-15·10.89·5e8 = 435.6 µW. If VDD scaled to 2.0 V, new P? Ans: ×(2/3.3)²=0.367 → 160 µW. (Why voltage scaling matters!)

7.4 DC Characteristics: NAND and NOR Gates (pp.260–266)

Same VM trick with effective β. Remember direction of shift.

⬆ Textbook — Fig 7.20 NAND2 VTC family: simultaneous curve is RIGHTMOST. Fig 7.21 layout for VM calc.

⬆ Textbook — Fig 7.25 NOR2 circuit + Fig 7.26 VTC family: simultaneous curve is LEFTMOST (opposite of NAND).

Merge trick (must write in exam):
• NAND2 simultaneous (VA=VB): series nFETs ≈ one (Wn/2L) → βn,eff=βn/2; parallel pFETs ≈ one (2Wp/L) → βp,eff=2βp. Plug into 7.14 with √(βn,eff/βp,eff)=(1/2)√(βn/βp).
• NOR2 simultaneous: parallel n → 2βn; series p → βp/2 → factor 2√(βn/βp).
• N-input: NAND factor (1/N), NOR factor (N).

V_M,NAND2-sim = [V_DD−|V_Tp| + ½√(βn/βp)·V_Tn]/[1+½√(βn/βp)] (7.94) ⭐
V_M,NAND-N: replace ½ by 1/N (7.95)
V_M,NOR2-sim = [V_DD−|V_Tp| + 2√(βn/βp)·V_Tn]/[1+2√(βn/βp)] (7.97) ⭐
V_M,NOR-N: replace 2 by N (7.98)

Memory hook: NAND = series-n weak → needs HIGHER Vin to pull down → shifts RIGHT. NOR = series-p weak → shifts LEFT. Order: VM,NOR-sim < VM,INV < VM,NAND-sim.

✅ Solved 7.4A — Problem [7.7] style

NAND2, βn=2βp (ratio 2, √=1.414), VDD=5, VTn=0.6, |VTp|=0.7.

Inverter: VM=(5−0.7+1.414·0.6)/2.414=(4.3+0.849)/2.414=2.13 V.

NAND2-sim: eff √=0.707. VM=(4.3+0.707·0.6)/1.707=(4.3+0.424)/1.707=2.77 V (+0.64 right shift ✓).

✏️ Try yourself 7.4B — Problem [7.8]

NOR2, βp=2.2βn → βn/βp=1/2.2=0.4545, √=0.674. VDD=3.3, VTn=0.65, |VTp|=0.8. Find simultaneous VM.

Ans: factor 2·0.674=1.348. VM=(3.3−0.8+1.348·0.65)/(1+1.348)=(2.5+0.876)/2.348=1.44 V. Inverter with same FETs would be (2.5+0.438)/1.674=1.755 V → left shift ✓.

7.5 NAND and NOR Transient Response (pp.266–272)

Worst-case philosophy + Elmore ladder. Draw subcircuits.

⬆ Textbook — Fig 7.29 NAND2 subcircuits: (a) rise via single Rp (worst), (b) fall via 2Rn ladder + Cx.

NAND2: C_out=C_par+C_L, C_par=C_dbn+2C_dbp (7.101–7.102)
Rise (worst, 1 pFET): τp=RpCout, tr=2.2τp, tr0=2.2RpCpar, αr=2.2Rp (7.105–7.109)

NAND2 fall (series): τn = C_out·2R_n + C_x·R_n = R_n(2C_out+C_x) (7.111–7.122) ⭐
t_f=2.2τn, t_f0=2.2Rn(2Cpar+Cx), α_f=4.4R_n (doubled!) (7.115–7.119)

NOR2: C_par=2C_dbn+C_dbp (7.124) · Fall (1 nFET): τn=RnCout, tf=2.2τn (like inverter) (7.125–7.130)
NOR2 rise (series): τp=C_out·2R_p+C_y·R_p, α_r=4.4R_p (7.131–7.138) ⭐

Worst cases (write this line, get marks): NAND rise = only ONE pFET on; NAND fall = BOTH nFETs on. NOR fall = only ONE nFET on; NOR rise = BOTH pFETs on. Always size for slowest. Series stacks are slow two ways: R adds (2R) + internal cap (Cx/Cy) adds term.

✅ Solved 7.5A — comparison (viva favourite)

Rn=1k, Rp=2k, Cout=80 fF, Cx=Cy=10 fF.

NAND rise: τ=2k·80f=160ps→tr=352ps. NAND fall: τ=80f·2k+10f·1k=170ps→tf=374ps (balanced).

NOR fall: τ=1k·80f=80ps→tf=176ps. NOR rise: τ=80f·4k+10f·2k=340ps→tr=748ps (skewed! series-p is worst because Rp already 2×Rn). Conclusion: prefer NAND, limit p-stacks.

✏️ Try yourself 7.5B — Problem [7.10]

NAND3 chain: Cout=130 fF, C1=C2=36 fF, βn=2.0 mA/V², VDD=3.3, VTn=0.6. (a) Elmore τ with internals? (b) ignoring C1,C2? %error?

Ans: Rn=1/[2e-3·2.7]=185 Ω. Ladder top→GND: τ=Rn(C1+C2+Cout)+Rn(C2+Cout)+Rn·Cout? For 3-stack discharging down: τ=Rn·C1′+… Standard: τ=185·(36+36+130)+185·(36+130)+185·130 =185·(202+166+130)=185·498=92.1 ps. Ignoring internals: τ=3·Rn·Cout? ≈185·3·130? No — Cout only through 3R: τ=3·185·130f=72.2 ps. Error=(92.1−72.2)/92.1=21.6% under-estimate. (Method matters more than exact number — show Elmore sum.)

7.6 Analysis of Complex Logic Gates (pp.272–276)

Same method on AOI/OAI. Plus activity factor α.

⬆ Textbook — Fig 7.32 complex gate f=x·(y+z): find longest series-n (fall) and series-p (rise).

Example: f = x·(y+z) (7.141) · τn=Cout·2Rn+Cx·Rn, tf=tf0+αfCL (7.144–7.147)
τp=Cout·2Rp+Cy·Rp, tr=tr0+αrCL (7.149–7.152)

P_dyn=α·C_outV_DD²f (7.154), α=P0·P1 (7.156)
α_NOR2=α_NAND2=3/16 (7.157–7.158) · α_NOR3=7/64 (7.159) · α_XNOR2=1/4 (7.160)

How to attempt any complex gate in exam: (1) Draw n-array, find longest series chain (worst fall). (2) Draw p-array (dual), find longest series chain (worst rise). (3) Write Elmore τ for each. (4) tr/tf=2.2τ. That's full marks even without numbers.

✅ Solved 7.6A — activity

NOR2, equiprobable inputs: P(out=0)=3/4 (only 00 gives 1), P(out=1)=1/4. α=3/4·1/4=3/16=0.1875. So Pdyn is only 18.75% of C·V²·f — big saving vs always-switching clock. XNOR2: P0=P1=1/2 → α=1/4.

7.7 Gate Design for Transient Performance (pp.276–281)

Design for speed first, check DC after. Reference = inverter.

⬆ Textbook — Fig 7.34 relative sizing: (a) inverter ref (βn,βp), (b) NAND2, (c) NOR2.

Ref inverter: β=k′(W/L) (7.161) · Symmetric βn=βp (7.163) → (W/L)p=(k′n/k′p)(W/L)n (7.164)

NAND2: βp(each)=βp,inv (1×); βn(each)=2·βn,inv (2×) (7.166–7.172) ⭐
NOR2: βn(each)=βn,inv (1×); βp(each)=2·βp,inv (2×) (7.173–7.176) ⭐
NAND3: n 3×, p 1×; NOR3: n 1×, p 3× (7.177–7.180) · General: n-series → n×

Rule in one sentence: Parallel FETs stay 1× (worst case uses one); series chain of n FETs → each n× so total R = inverter R. Cost: area + bigger Cpar/Cx — diminishing returns for long stacks (Ch.8 fixes with staging/logical effort).

✅ Solved 7.7A

k′n/k′p=2.5, inv (W/L)n=2. Symmetric → (W/L)p=2.5·2=5. NAND2: p each=5 (1×), n each=2·2=4 (2×). NOR2: n each=2, p each=2·5=10. Note NOR pFETs huge — reason NAND preferred.

✏️ Try yourself 7.7B — Problems [7.11]–[7.13] pattern

F=a·b+c·d·e (AOI). Inv ref βn=βp. Size for equal R? Ans: Longest n-discharge = 3 series? (c·d·e) → all n 3×. Worst p-charge = 2 series (a,b side + c,d side in dual) → those p 2×, solo p 1× (or 2× uniform). Draw both arrays to justify.

7.8 Transmission Gates and Pass Transistors (pp.281–285)

No rail → no restoration → threshold drop. Favourite short-note Q.

⬆ Textbook — Fig 7.37 TG (n+p parallel) + RC model RTG.

⬆ Textbook — Fig 7.39 nFET pass waveforms: output capped at Vmax, tr≈6·tf.

R_TG=max(R_n,R_p) (7.186) · C_in=C_Sn+C_Dp (7.187)

nFET pass logic-1: V_max=V_DD−V_Tn (never reaches VDD!) (7.189–7.190)
t_r=18τn (0→0.9Vmax, rational not exponential) (7.192) · t_f≈2.94τn (clean to 0) (7.195) · t_r≈6t_f (rise-limited) (7.196)

pFET dual: passes strong 1 (VDD, tr=2.94τp) (7.197) but logic-0 stalls at V_min=|V_Tp| (7.199), fall-limited (7.200)

✅ Solved 7.8A — Problems [7.14]/[7.15] style

VDD=5, VTn=0.5, βn=1.5 mA/V², Cout=84 fF, logic-1 in, cap empty. Rn=1/[1.5e-3·4.5]=148 Ω. τn=148·84f=12.4 ps. tr=18·12.4=224 ps to 0.9·4.5 V. Vmax=4.5 V. Switch to 0: tf=2.94·12.4=36.5 ps. Ratio ≈6 ✓.

pFET: W/L=8, k′p=60µ, VDD=3.3, |VTp|=0.8, Cout=50 fF, cap at VDD→in 0. βp=480µ, Rp=1/[480e-6·2.5]=833 Ω, τp=41.7ps. Fall (limited, to |VTp|): slow; rise back: tr=2.94·41.7=122.5 ps.

7.9 Comments on SPICE Simulations (pp.285–288) — viva only

No numerical. Know 4 commands + 1 example.

Why simulate: hand calcs use square-law + step input + voltage-independent C — estimates only. Tape-out needs SPICE (watch convergence/noise).
Netlist: M1 D G S B MODEL W= L=, order Drain-Gate-Source-Bulk. Add AD/PD/AS/PS (area/perim) by hand if extractor omits.
Sources: PULSE(V1 V2 TD TR TF PW PER), EXP(...). Analyses: .DC VIN 0 VDD STEP (VTC), .TRAN TSTEP TSTOP.
Ex 7.5: shared 10×8 region (A=80, P=36) split e.g. AS=40P/PS=18U + AD=40P/PD=18U (equal) or 10/70 split — both valid if totals ≤ real.

📋 Master formula sheet (print this — 1 page)

All equations with book numbers. Revise by covering right column.

#	Formula (what to write)	When / meaning
7.1–7.3	VOH=VDD, VOL=0, VL=VDD	Full-rail endpoints
7.8	NML=VIL−VOL, NMH=VOH−VIH	Noise margins (slope −1 pts)
7.14 ⭐	VM=[VDD−\|VTp\|+√(βn/βp)·VTn]/[1+√(βn/βp)], β=k′(W/L)	Inverter threshold — #1 asked
7.20	Symmetric (VTn=\|VTp\|): βn=βp → Wp/Wn=k′n/k′p≈2–3	Centred VTC
7.28 ⭐	Rn=1/[βn(VDD−VTn)], Rp=1/[βp(VDD−\|VTp\|)]	FET resistors
7.32	Cout=Cpar+CL, Cpar=Cdbn+Cdbp	Total load
7.48/54 ⭐	tf≈2.2RnCout, tr≈2.2RpCout	90–10% times
7.55	fmax=1/(tr+tf)	Max toggle
7.65–66	t50%=0.69τ, tp=(tPHL50+tPLH50)/2	Prop delay
7.69–72	tr=tr0+αrCL, tf=tf0+αfCL; tr0=2.2RpCpar; αr=2.2Rp (same f)	Load sweep
7.91–92 ⭐	Pdyn=CoutVDD²f, P=PDC+Pdyn, PDC=VDDIDDq	Power
7.94/95	VM,NAND: √(·)→(1/N)√(βn/βp) — shifts RIGHT	NAND DC
7.97/98	VM,NOR: √(·)→N√(βn/βp) — shifts LEFT	NOR DC
7.111	NAND fall: τn=Cout·2Rn+Cx·Rn, αf=4.4Rn	Series-n delay
7.134	NOR rise: τp=Cout·2Rp+Cy·Rp, αr=4.4Rp	Series-p delay
7.154	Pdyn=αCV²f; αNOR2=3/16, αXNOR=1/4	Activity
7.171–176	NAND: n 2× p 1×; NOR: n 1× p 2×; N-in: series N×	Sizing
7.186–196	RTG=max(Rn,Rp); n-pass Vmax=VDD−VTn, tr=18τn, tf=2.94τn, tr≈6tf	TG/pass

🖨️ Print formula sheet

📝 Numerical bank — solved + exam drills (with textbook problems verbatim)

Do solved first (answers open), then closed-book drills. Problems [7.x] are verbatim from pp.288–291.

A. Solved drills (one per section — done above, quick links)

7.1A (VM/sizing), 7.2A (tr/tf/fmax), 7.3A (power), 7.4A (NAND shift), 7.5A (NAND vs NOR), 7.6A (α), 7.7A (sizing), 7.8A (pass FET) — all with full steps above. Re-solve each in <5 min.

B. Textbook problems — attempt these (starred = your listed Exercises 2,3,5,6,14,15)

[7.2] ⭐, [7.3] ⭐, [7.5] ⭐, [7.6] ⭐, [7.14] ⭐, [7.15] ⭐ + rest — click to see full statements & hints

[7.1] k′n=100µ, VTn=0.70, k′p=42µ, VTp=−0.60, VDD=3.3, (W/L)n=10,(W/L)p=14. Find VM. → 7.14 direct.

[7.2] ⭐ (your Ex-2) Find βn/βp for VM=1.3 V, VDD=3 V, VTn=0.6, VTp=−0.82. Relative sizes if k′n=110µ, µp=µn/2.2? Hint: invert 7.14: √(βn/βp)=(VDD−VM−|VTp|)/(VM−VTn). Ans: √=(3−1.3−0.82)/(1.3−0.6)=0.88/0.7=1.257→ratio=1.58.

[7.3] ⭐ (your Ex-3) βn=2.1m, βp=1.8m, VTn=0.6, VTp=−0.7, VDD=5, Cpar=74f. (a) VM (b) Rn,Rp (c) tr,tf at CL=0 (d) at CL=115f (e) plot vs CL. → solved 7.2B above.

[7.4] VM for Fig 7.11 layout. → extract (W/L) from layout, apply 7.14.

[7.5] ⭐ (your Ex-5) Fig 7.11 + CL=80f, Lelec=0.8µm. (a) Cin (b) Rn,Rp (c) tr,tf. → Cin=Cg sum; R via 7.28; t via 2.2RC.

[7.6] ⭐ (your Ex-6) SPICE Fig 7.11, CL=100f, DC+transient. → deck in 7.9; compare VM/tr with hand calc.

[7.7] NAND2 βn=2βp, VDD=5, VTn=0.6, VTp=−0.7. (a) simultaneous VM (b) inverter VM same β. → solved 7.4A.

[7.8] NOR2 βp=2.2βn, VDD=3.3, VTn=0.65, VTp=−0.8. Simultaneous VM. → try 7.4B.

[7.9] NAND3 n W/L=4 each, k′n=120µ, VTn=0.55, VDD=5, want simultaneous VM=2.4, VTp=−0.9, r=2.4. Find βp. Hint: 7.95 with N=3, solve for √(βn/βp).

[7.10] NAND3 chain Cout=130f, C1=C2=36f, βn=2m, VDD=3.3, VTn=0.6. Elmore τ? Ignore C1,C2? %error? → try 7.5B.

[7.11]–[7.13] Complex sizing (AOI/OAI: F=a·b+c·d·e etc.). → method in 7.6/7.7: longest chain → n×.

[7.14] ⭐ (your Ex-14) n-pass βn=1.5m, VDD=5, VTn=0.5, Cout=84f, uncharged. (a) τ (b) tr (c) switch to 0: tf (d) SPICE. → solved 7.8A: τ=12.4ps, tr=224ps, tf=36.5ps.

[7.15] ⭐ (your Ex-15) p-pass W/L=8, k′p=60µ, VDD=3.3, VTp=−0.8, Cout=50f, cap at VDD→in 0. (a) tf (b) back to VDD: tr. → solved 7.8A: tr≈122ps, fall limited to |VTp|.

C. 5-min mock (closed book — predict your quiz)

Q1 (4m): Inverter k′n=120µ,k′p=50µ,VTn=0.6,|VTp|=0.7,VDD=3V,(W/L)n=4,(W/L)p=6. Find VM + size for symmetric.
Q2 (4m): Same inverter, Cout=200fF. Find Rn,Rp,tr,tf,fmax.
Q3 (2m): NAND2 with same FETs — simultaneous VM? Left or right of inverter? Why? + Pdyn if Cout=200f,VDD=3,f=200MHz.

Check answers

Q1: βn=480µ,βp=300µ,ratio=1.6,√=1.265,VM=(3−0.7+1.265·0.6)/2.265=(2.3+0.759)/2.265=1.35V. Symmetric: Wp/Wn=120/50=2.4 → need (W/L)p=2.4·4=9.6.

Q2: Rn=1/[480e-6·2.4]=868Ω, Rp=1/[300e-6·2.3]=1449Ω. τn=173.6ps→tf=382ps; τp=289.9ps→tr=638ps; fmax=0.98GHz.

Q3: eff√=0.632,VM=(2.3+0.632·0.6)/1.632=1.64V (right of 1.35 ✓ series-n). Pdyn=200e-15·9·2e8=360µW.

⚠️ Traps & final checklist

Top 6 traps
1. VDD vs Vpp same; |VTp| positive in formulas (don't plug −0.7).
2. β=k′(W/L) — multiply BEFORE ratio, watch µA→A (×1e-6).
3. tr uses Rp, tf uses Rn (crossed!).
4. 2.2 for 10–90%, 0.69 for 50% — don't swap.
5. NAND→right, NOR→left (simultaneous). Parallel=1×, series=n×.
6. Pass FET: n can't pass 1 (Vmax=VDD−VTn, tr=18τ); p can't pass 0 (Vmin=|VTp|).

Night-before checklist
☐ Write 7.14 from memory
☐ Write 7.28 + 2.2/0.69
☐ Write Pdyn + sizing rules
☐ Re-solve 7.1A + 7.2A without peeking
☐ Read all figure captions once
☐ Sleep — VM shifts are easy marks when fresh.

Sources: all equations/derivations/figures from Uyemura Ch.7 pp.237–288 (PDF pp.253–305). Page renders in ch7_figs/ are full textbook pages — zoom to read fine print. Course Plan: 23ECE302 Unit II (Lec 20–28). Good luck! ⚡

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